Proposed topology of cascaded multilevel inverter used for reduced number of on state switches

Abstract

This paper presents a novel topology for cascade multilevel inverter. Multilevel inverter is an alternative within the area of lot of power average voltage energy control. This proposed paper analyses a generalized cascaded inverter topology with minimized number of switching devices. In this proposed work of multilevel inverter, the aim is to reduce the number of dc voltage sources and switches to obtain number of voltage levels. The proposed circuit consists of series connected Switching units and it can generate DC voltage levels similar to other topologies. In this paper, six switches are used to generate 9 level inverter output. Topology of the proposed cascaded multilevel inverter considers some factors such as number of switching devices, number of output voltage levels and the standing voltage on the switches. The quality output voltage depends on the number of voltage level in the inverter. This new inverter shows superior capabilities when compared to other existing topologies. To verify the proposed topology, a 9-level inverter has been simulated. In this work the THD value is reduced to 7.58 % which is very low when compared to other existing topologies. The simulation results are carried out using MATLAB/SIMULINK.