Carry-based reduction parallel counter design

Abstract

Parallel counters are one of the important components to construct high performance DSP units including column compression multipliers (i.e. tree multipliers). As the multiplier size increases, designing optimised wider counters is critical for its performance, which is the motive of this study. This article proposes a novel approach to design (2 n −1, n) parallel counter using a reduction stage and a single (2 n −1 −1, n − 1) parallel counter. An algorithm to construct the reduction stage for any counter size is presented. The designs of parallel counter examples using the proposed algorithm are discussed. Finally, the proposed design performance metrics (in terms of delay, power and energy-delay-product) are compared with the conventional parallel counter designs. The proposed designs achieve 13% average speed up, 10% power reduction and 32% improvement in energy-delay-product compared with conventional counters.