CAPMIG: Coherence-Aware Block Placement and Migration in Multiretention STT-RAM Caches

Abstract

In recent years, the increased working set size of applications craves more memory demand in terms of large-sized last-level caches (LLCs). To fulfill this, one of the promising technology is STTRAM. However, high write energy and write latency make it challenging to adopt it on a wide scale. Multiretention STTRAM caches have been considered an improvisation over standard STTRAM caches by reducing their retention time which reduces the write latency. Here, we have to negotiate with a refresh operation by applying various refresh management techniques. However, its retention period consumes significant refresh energy in the periodic refresh. In this article, we take help from the coherence protocol and decide the best retention type for each block. A block loaded on a write access is likely to get more writes in the future and is therefore loaded in the lowest retention time region. Similarly, instruction blocks are loaded in the highest retention time region. This helps in reducing the number of refreshes incurred by the blocks. During runtime, the blocks may change their access patterns, requiring a change in their retention region. This article also proposes a migration policy to relocate the blocks to appropriate regions during runtime. Identification of zero data value blocks and not refreshing them is an additional augmentation to our proposal. The experimental result using full system simulation shows a good reduction in the number of refreshes and energy consumption over the baseline designs.