Retention-Aware Refresh Techniques for Reducing Power and Mitigation of Data Retention Faults in DRAM

Abstract

Due the leakage mechanisms exist in DRAM cells, DRAM cells lose stored information over time. Periodic refresh operations are inevitable for retaining the stored information. However, refresh operations are very power hungry and impact the bandwidth substantially since the refresh period is usually determined by the leakiest DRAM cells. A straightforward way for reducing refresh power is by merely extending the single standard refresh period. The incurred side effect is that more data retention faults (DRFs) will be generated and the fabrication yield will be sacrificed. To cure these dilemmas, a novel address remapping technique—the sub-bank address remapping (SBAR) technique is proposed in this paper. SBAR manipulates the logical-to-physical address remapping for each sub-bank such that the leakiest cells can be clustered and refreshed with their most suitable refresh periods. For the majority of DRAM cells, they can be refreshed with a longer refresh period such that the refresh power can be effectively reduced. The corresponding hardware architectures are also proposed. Experimental results show that we can respectively save 74.97% refresh power with less than 0.1% hardware overhead for a 1-Gb DRAM. Moreover, the fabrication yield can also be improved significantly.