Adaptive block-based refresh techniques for mitigation of data retention faults and reduction of refresh power

Abstract

The distribution of data retention time of DRAM cells heavily dominates the refresh power consumption and fabrication yield. Although merely extending the single standard refresh period can effectively reduce the refresh power, however, it will incur more data retention faults (DRFs). In this paper, a novel sub-bank address remapping (SBAR) technique is proposed to cure this dilemma. Memory blocks can be refreshed adaptively based on the profile of their data retention time. SBAR uses control words for logical-to-physical address remapping such that the leakiest cells can be clustered and refreshed with their most suitable refresh periods. A refresh configuration word is used in the refresh counter for determining the length of refresh period for each memory block. For the majority of DRAM cells, they can be refreshed with a longer refresh period such that the refresh power can be effectively reduced. The corresponding hardware architecture is also proposed. Experimental results show that we can save 74.97% refresh power with less than 0.1% hardware overhead for a 1-Gb DRAM. Moreover, if there are no any repair or error correction techniques incorporated and we decrease the standard refresh period from 64 ms to 32 ms, 16 ms, or 8 ms for cells containing data retention faults, the yield can be improved 0.68, 0.96, and 1.09 times, respectively.