Capacitance-voltage technique for characterization of lateral trap locations along the channel in low-temperature poly-silicon thin film transistors

Abstract

This study introduces a characterization technique for trap locations (Xt) with considerable trap density along the channel in field effect transistors (FETs). The technique is based on the experimental gate-to-source or gate-to-drain capacitance-voltage (CGS-VGS or CGD-VGD) characteristics of FETs. As the gate bias (VG) increases, the effective channel length (Leff) extends by the increased conductivity of the channel from the source or the drain. Due to trapped charges at the trap sites with a high density of traps along the channel, abrupt change in the C-V characteristics is observed. For the transition gate bias (VG,t) with abrupt change in the C-V characteristics, the dominant trap location (Xt) can be converted through the channel conduction factor (α(VG) to be the effective channel length Leff(VG) = α(VG)∙Lch). We expect that the proposed C-V technique to be useful in non-destructive electrical characterization of lateral trap locations (interface states, bulk traps, and/or grain boundary traps caused by the bias stress and/or fabrication process) along the channel in FETs. We successfully applied the proposed technique to the p-channel poly-Si thin-film transistors (TFTs) for characterization of the grain boundary locations along the channel. As an example for the proposed technique, we applied the technique to a p-channel poly-Si TFT and obtained a dominant trap at XGB1 = 3.13 [μm] from the source and another at XGB2 = 3.70 [μm] from the drain.