Bump & assembly technologies for sub-100 micron pitch flip chip

Abstract

Excepting Au bumped tape automated bonded (TAB) liquid crystal display driver chips, the goal of sub 100 /spl mu/m pitch flip chip remains elusive. Well understood advantages include die shrink opportunity as well as speed and performance enhancement. However, perhaps the greatest advantages lie in reduced substrate layer count (with accompanying cost reduction) and routing simplification leading to better impedance control capabilities. In order to cost effectively take advantage of these opportunities, fine pitch flip chip technologies compatible with both today's bumping infrastructure and today's substrate capabilities must be identified. This paper compares and contrasts four alternative solutions for sub-100 /spl mu/m flip chip bumping and assembly, including traditional Au tape carrier packages (TCP), stud bump bonding (SBB) in combination with modern high density interconnect (HDI) substrates, Integrated Electronic Package Technologies' (IEPT) plated Cu bump technology with traditional HDI substrates, and the very recently introduced capillary chip connection (C3) from Microelectronics Assembly Innovations (MAINn).