Challenges and approaches of ultra-fine pitch Cu pillar assembly on organic substrate using wafer level underfill

Abstract

The use of flip-chip technology in packaging interconnects is becoming more important due to its better electrical performance, smaller form factor packages, and higher interconnect density than wire bonded packages. Flip-chip soldering has been the mainstream flip-chip technology. However, the move towards fine pitch Cu pillar flip chip packaging with fine pad bond pitch has driven the investigation of Sn plated bumps on Cu pillar encapsulated with wafer level underfill as a potential alternative [1]. As the pitch of the electrical interconnections decreases and chip size increases, it is more difficult to develop high through-put processes using conventional capillary flow underfills. A WLUF process eliminates the time required to dispense conventional underfill to every chip and for capillary flow [2]. Fillers are used in underfill materials to decrease the coefficient of thermal expansion (CTE) which has the effect of reducing package stresses, and helping to achieve better reliability performance. However, in the case of WLUF with high filler content, it is very challenging to achieve 100% electrically and metallurgically good Pb-free solder joints and void-free underfill as the epoxy based WLUF can cure early, below the Pb-free solder melting temperature, and become trapped between flip chip bumps and substrate solder pads. Also, the high process temperature of Pb-free solder can cause a large amount of voids to form within the WLUF material during the solder joining cycle [3-4]. In the paper, a WLNCF with 40% fillers was laminated onto 8 inch wafer containing Cu pillar post with Sn solder bumps by spin coating. The wafer was diced into chips. A chip was aligned and joined to a substrate with an optimized heating and cooling cycle. The effects of the bonding parameters and bonding temperature profile on the fine pitch flip chip assembly on solder wetting, solder joint shape and WLNCF voids are addressed in this paper. The main challenge for the fine pitch flip chip assembly was to assemble a fine pitch Cu pillar assembly onto an organic substrate while ensuring good solder wetting, good bonding placement accuracy, minimum solder joint voids, good fillet coverage and no wafer level underfill trapped between the solder and substrate bond pad after thermocompression bonding. In addition, wafer level underfill lamination uniformity and voids after lamination and B-stage cure were inspected. Wafer dicing evaluation was also performed to ensure no debris or particles adhering to the WL-NCF during dicing. No peeling or delamination of the WL-NCF was observed after dicing. The impact of these various factors on the stacked die assembly is discussed in this paper.