Abstract
This paper describes a Prolog based Block Extraction System (ProBES) which converts a transistor level description of a CMOS circuit into a logic block level description. The operation of ProBES is conceptually similar to that of a circuit extractor. However, whereas a circuit extractor is used to identify circuit primitives such as transistors, resistors and capacitors from the geometrical information in a mask level layout description, ProBES can be used to identify predefined gates and logic blocks in a CMOS transistor network. ProBES operates according to the circuit hierarchy. Basic gates such as inverters, transmission-gates, nands, nors, etc. are identified first. Logic blocks composed of these gates are then identified. More complex blocks which contain blocks already identified are recognized next and so on. ProBES is meant to be used as an aid in the verification of logic design. It can provide a connectivity check for a circuit.
Highlights
This paper describes a Prolog based Block Extraction System (ProBES) which converts a transistor level description of a CMOS circuit into a logic block level description
We describe a method to recognize logic functional blocks from a transistor level description of a circuit
Variables may be instantiated to constants which begin with lower-case letters.) The derived expressions at the output node of a logic block are in terms of Prolog constants
Summary
Significant aspect of the VLSI design process is verifying that the final layout correctly represents the intended logic. A system has been implemented to automatically extract logic blocks from a CMOS transistor level description. We describe a method to recognize logic functional blocks from a transistor level description of a circuit. An intelligent program attempting to recognize logic blocks in a circuit would need a knowledgebase which enables it to do the following: Correlate derived boolean expressions with defined functions. The transistor level description of the circuit is processed to a form where the application of recognition rules can proceed This processing step involves partitioning a circuit into smaller subcircuits and extracting logic expressions at output nodes of these subcircuits. The early recognition of inverters is necessary to identify complementary signals in the circuit This information is useful in later steps when logic expressions are derived at the output nodes of partitioned blocks. It does not always conform to the usual notion of a pullup node in a CMOS circuit as a node connected to vdd via a p block
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