Abstract
Processes such as polysilicon emitter, various self-alignment schemes, and deep trench isolation have led to significant improvements in intrinsic speed and reductions in parasitic RC elements in silicon BJT (bipolar junction transistor) devices. Some basic physical limitations involved in further scaling the intrinsic device vertical profile for silicon BJTs are discussed. Also presented is a review of recent developments in silicon-based heterojunction bipolar transistors which have the potential of overcoming some of the basic limitations in homojunction BJTs. >
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