Abstract
This paper focuses on the analysis of InGaZnO thin-film transistors (TFTs) and circuits under the influence of different temperatures and bias stress, shedding light into their robustness when used in real-world applications. For temperature-dependent measurements, a temperature range of 15 to 85 °C was considered. In case of bias stress, both gate and drain bias were applied for 60 min. Though isolated transistors show a variation of drain current as high as 56% and 172% during bias voltage and temperature stress, the employed circuits were able to counteract it. Inverters and two-TFT current mirrors following simple circuit topologies showed a gain variation below 8%, while the improved robustness of a cascode current mirror design is proven by showing a gain variation less than 5%. The demonstration that the proper selection of TFT materials and circuit topologies results in robust operation of oxide electronics under different stress conditions and over a reasonable range of temperatures proves that the technology is suitable for applications such as smart food packaging and wearables.
Highlights
InGaZnO thin-film transistors (IGZO TFTs) enable uniformity over large-areas, compatibility with low-cost and low-temperature fabrication techniques, and high mobility (>10 cm2 /V·s), setting oxideTFTs as a winning alternative for flexible large area electronics (LAE) when compared to competingTFT technologies (e.g., a-Si:H and poly-Si) [1]
In oxide TFTs, VTH variation with gate bias stress is due to the charge trapping at the semiconductor dielectric interface or charge getting into the dielectric [8,9,10]
Oxide TFTs show positive VTH shift under positive gate bias stress due to charge trapping at the semiconductor/dielectric interface or charge getting into the dielectric [8,9,10]
Summary
InGaZnO thin-film transistors (IGZO TFTs) enable uniformity over large-areas, compatibility with low-cost and low-temperature fabrication techniques, and high mobility (>10 cm2 /V·s), setting oxide. Despite the high relevance of these studies to gain insights on device physics, the works in this area are typically based on oxide TFTs annealed at high temperatures (>300 ◦ C), which are more stable than low-temperature ones but are not compatible with low-cost flexible LAE concepts. The current work presents for the first time a unified characterization of low-temperature (180 ◦ C) oxide TFTs and circuits behavior under bias stress and temperatures ranging from 15 to 85 ◦ C. Circuits (inverter and current mirrors) have shown a robust performance by compensating these IDS shifts, even if a low-temperature oxide TFT process is used (180 ◦ C), which leads to lower TFT performance and more device-to-device variation than what is typically obtained with high-temperature processing (>300 ◦ C).
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