Abstract
Bias optimization is one of the most important design issues in many low power applications. Several biasing schemes for switched capacitor applications are analyzed in this paper from the settling time point of view. A bias circuit is described that provides the best tradeoff between the slew-rate and the unity gain bandwidth of a single dominant-pole opamp over process and temperature variations. Theoretical analysis and simulations confirm a quasi-constant settling time with minimal process dependence.
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