Abstract
In this article, we present a cross-layer optimization and benchmarking of various spintronic memory devices, including spin-transfer-torque magnetic random access memory (STT-MRAM), spin-orbit-torque (SOT) MRAM, voltage-controlled exchange coupling (VCEC) MRAM, and magnetoelectric (ME) MRAM. Various material, device, and circuit parameters are optimized to maximize array-level READ and WRITE performances and to benchmark spintronic devices against static random access memory (SRAM). It is shown that the optimized parameters, such as magnetic tunnel junction (MTJ) oxide thickness or transistor size, are quite different for various device options. The optimal oxide thickness of VCEC-MRAM is 1.6 nm because it is a voltage-controlled device; thus, thicker oxide gives smaller READ energy-delay product (EDP), whereas, for STT-MRAM, the optimal oxide thickness is 1.3 nm to keep the WRITE voltage low while avoiding READ disturbs. In addition, we find that the co-optimization of material, device, and circuit analyses are critical because it is not enough to identify the most promising material for various device options with only material- or device-level metrics. For instance, SOT materials with the highest spin conductivity may not result in the best array-level WRITE performance because of their large resistivity and, in some cases, READ disturb issues. We also present a new design and cell layout for ME-MRAM in which the number of access transistors depends on the WRITE voltage. The benchmarking results show that SOT-MRAM can be fast and low energy but would suffer from a 25% larger cell area compared with STT-MRAM. VCEC-MRAM can be denser than STT-MRAM (2T1MTJ) and dissipate less energy but would suffer from slower READ operations because of its large oxide thickness. ME-MRAM can be fast, low energy, and dense compared with all other options.
Highlights
S PINTRONIC devices are promising candidates for embedded memory due to their nonvolatility and small footprint compared with static random access memory (SRAM) [1]
They offer high endurance and faster WRITE operations compared with resistive random access memory (RRAM) and embedded nand flash and better scalability of their WRITE currents compared with phase-change memory (PCRAM) [2]
To compare the performances of spintronic memory devices in the embedded memory application, we simulate the READ and WRITE performances of SRAM considering that the fin ratio of the pull-down, pass gate, and the pull-up transistors is 1:1:1 using a 16-nm predictive technology model (PTM) established by Arizona State University [23]
Summary
S PINTRONIC devices are promising candidates for embedded memory due to their nonvolatility and small footprint compared with static random access memory (SRAM) [1]. The fact that the WRITE and READ currents pass through the same path does not allow for the independent optimization of the READ and WRITE operations To address these challenges, other MRAM device options have been proposed based on various WRITE mechanisms, such as spin-orbit torque (SOT-MRAM), voltage-controlled magnetic anisotropy (VCMA-MRAM) [5], voltagecontrolled exchange coupling (VCEC-MRAM) [6], and magnetoelectric effect (ME-MRAM) [7]. The ab initio calculations show that the applied voltage close to the oxide interface can modulate the interlayer exchange coupling in the synthetic antiferromagnet, changing the magnetization direction of the free ferromagnet [6] Another candidate is ME-MRAM that uses multiferroic materials, such as BiFeO3 [11], [12] or Cr2O3 [13], in contact with a free ferromagnet of an MTJ.
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