Abstract
this paper, a synthesis for testability approach is resented. In this approach we select test points or gip-flops to be used in Test Point Insertion or Par- tial Scan to enhance circuit testability. The selection is based on circuit behavioral information rather than low level structural description. This allows Test Point Insertion or Partial Scan usa e on circuits described as interconnection of high levefmodules. In this pa er we also pro ose Test Statement Insertion as an aier; native to &st Point Insertion and to Partial Scan. The major advantage of using Test Statement Inser- tion is less pin count and lower test application time overhead than Test Point Inserti0.n and Partial Scan. Our tool has been implemented in a computer pro- gram.
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