Abstract
A synthesis for testability approach is presented. In this approach test points or flip-flops to be used in test point insertion or partial scan to enhance circuit testability are selected. The selection is based on circuit behavioral information rather than low level structural description. This allows test point insertion or partial scan usage on circuits described as interconnections of high level modules. Test statement insertion is also proposed as an alternative to test point insertion and to partial scan. The major advantage of using test statement insertion is a lower pin count and lower test application time overhead than test point insertion and partial scan. The tool has been implemented in a computer program. >
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