Zero Cost Test Point Insertion Technique for Structured ASICs

Abstract

We show different ways in which unused multiplexers (MUXes) and scan flip-flops (flops) in a structured application specific integrated chip (SA) design can be re-configured to insert test points to drastically reduce test volume and test generation time. We convert unused hardware in SAs into: (a) conventional control points, (b) complete test points, (c) pseudo-control points or (d) inversion test points. Since only unused hardware is used, the proposed test point insertion (TPI) technique does not entail any extra hardware overhead. Test points are inserted using timing information, so they do not degrade performance. We also present novel gain functions that quantify the reduction in test volume and automatic test pattern generation (ATPG) time due to TPI and are used as heuristics to guide the selection of signal lines for inserting test points. Experimental results clearly demonstrate the effectiveness and scalability of the proposed technique. Using very little unused hardware and TPI run time, we reduced ATPG time by up to 63.1 % and test data volume by up to 64.5% while also achieving a near 100% fault efficiency for very large industrial designs