Efficient test mode selection and insertion for RTL-BIST

Abstract

Inserting test logic at the Register Transfer Level (RTL), instead of at the gate-level, offers many advantages. It allows the synthesis process to consider both functional and test logic together for optimization for meeting the timing/area/power goals; thus, this avoids an expensive cycle of re-optimization. It is also a necessary step for supporting RTL signoff. In this paper, we present a Built-in Self-Test (BIST) framework that allows efficient selection and insertion of test points at the RT level for achieving high fault coverage. We discuss the need for a new type of test points, called operator test points, in order to achieve high fault coverage for RTL BIST. The traditional node test points and the operator test points are jointly called test modes in this paper. We present a test-mode selection algorithm at the RT level, which uses a hybrid cost function derived from controllability, observability (C/O) and testability gradients of signals. Experimental results on some industrial designs indicate that high fault coverage can be achieved for various implementations of an RTL design by selecting and inserting the test modes at the RT-level.