BAS: A BTI-based aging aware synthesis in FPGAs

Abstract

Aging mechanisms in FPGA devices cause performance degradation and lead to lifetime reduction. Among multiple aging mechanisms, Biased-Temperature-Instability (BTI) aging mechanism is the dominant one. BTI decreases the Static-Noise-Margin (SNM) of SRAM cells leading to more Soft-Error-Rate (SER) and lower SRAMs’ stability in FPGAs. This paper proposes the BAS (BTI Aware Synthesis), a three-step post-synthesis and pre-place-and-route tool to reduce the impact of BTI in FPGA’s LUTs significantly using the Bit-Flipping and Boolean Matching techniques. BAS receives a standard EDIF format synthesis output file from a synthesis tool (e.g., C.edf) and finally creates two output EDIF files with the same functionality as the original input file (e.g., C1.edf and C2.edf), while all LUT SRAMs contents are mutually flipped. The two BTI-Aware-created EDIF synthesis files are periodically used for FPGA’s reconfiguration. Our experimental results demonstrates that BAS improves SNM and SER on average by 16.1% and 15.7% compared to previous state-of-the-art techniques, respectively. BAS has two main advantages over previous state-of-the-art techniques: (1) it is more flexible and applicable as an embedded tool within worldwide commercial synthesis tools, and (2) unlike the previous state-of-the-art techniques, it does not need the map and details of the FPGAs.