Balanced ternary addition using a gated silicon nanowire

Abstract

Ternary logic has the lowest cost of complexity, here, we demonstrate a CMOS hardware implementation of a ternary adder using a silicon metal-on-insulator single electron transistor. Gate dependent rectifying behavior of a single electron transistor (SET) results in a robust three-valued output as a function of the potential of the single electron transistor island. Mapping logical, ternary inputs to the three gates controlling the potential of the single electron transistor island allows us to perform complex, inherently ternary operations, on a single transistor.