Balanced codes for data retention of multi-level flash memories with fast page read

Abstract

Flash memories use the amount of charge (e.g., electrons) trapped in floating gate transistors to represent data. Charge leakage will cause data retention problem by unidirectionally shifting the cell-level distribution. Balanced codes are an effective means to adjust read thresholds adaptively and tolerate the charge leakage under unknown retention environments. For multi-level cell (MLC) flash memories with 4 levels, 2 binary logical pages are mapped to one quaternary physical page. In order to achieve a small read latency, one (or two, respectively) read threshold(s) is (are) applied to the physical page to retrieve data for the least significant bits (LSBs) (or most significant bits (MSBs), respectively). In this paper, we propose two coding schemes that use balanced codes for multi-level flash memories, which tolerate charge leakage and provide fast page read simultaneously. We prove that our coding schemes asymptotically bring no rate penalty (2 bits/cell for quaternary cells). We establish a model of the programming, retention, and read for MLC, then theoretically calculate the raw bit-error-rate (RBER) and page-error-rate (PER), and compare the performance of read threshold adjustments based on balanced codes and the conventional scheme that estimates the cell level drift. It is shown that for a fixed PER, the requirement for error correction codes (ECCs) when using balanced codes is much less than that of using conventional schemes, which has the benefits of ECC rates, decoding delay, and decoding complexity.