Abstract
Abstract In 1 M-bit/cell multi-level cell (MLC) flash memories, it is more difficult to guarantee the reliability of data as M increases. The reason is that an M-bit/cell MLC has 2 M states whereas a single-level cell (SLC) has only two states. Hence, compared to SLC, the margin of MLC is reduced, thereby making it sensitive to a number of degradation mechanisms such as cell-to-cell interference and charge leakage. In flash memories, distances between 2 M states can be controlled by adjusting verify levels during incremental step pulse programming (ISPP). For high data reliability, the control of verify levels in ISPP is important because the bit error rate (BER) will be affected significantly by verify levels. As M increases, the verify level control will be more important and complex. In this article, we investigate two verify level control criteria for MLC flash memories. The first criterion is to minimize the overall BER and the second criterion is to make page BERs equal. The choice between these criteria relates to flash memory architecture, bits per cell, reliability, and speed performance. Considering these factors, we will discuss the strategy of verify level control in the hybrid solid state drives (SSD) which are composed of flash memories with different number of bits per cell.
Highlights
Flash memory is the fastest growing memory segment, driven by the rapid growth of mobile devices and solid state drives (SSD)
error control coding (ECC) encoding and decoding are performed in page units [13-15]. It means that the word error rate (WER) of each page depends on each page bit error rate (BER) which corresponds to p in (31)
Criterion 1 can minimize the overall BER, it requires interleaving in multipage architecture which reduces the speed performance
Summary
Flash memory is the fastest growing memory segment, driven by the rapid growth of mobile devices and solid state drives (SSD). M-bit/cell MLC flash memories have 2M states within the threshold voltage window whereas the single-level cell (SLC) has only two states. The incremental step pulse programming (ISPP), which is the most widely used programming scheme, was proposed to maintain a tight cell threshold voltage distribution for high reliability [7,8]. ISPP can control both the distances between states by verify levels and the tightness of program states by the incremental step size. The verify level control issue for M-bit/cell flash memories is more important and complex than that for SLC. This is because 2M states have to be crammed within
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