Background Calibration of Comparator Offsets in SHA-Less Pipelined ADCs

Abstract

Sample-and-hold amplifier-less (SHA-less) pipelined analog-to-digital converters (ADCs) are well suited for high-resolution, high-speed and low-power applications. Apart from the comparator static offset, a dynamic offset is induced due to the timing skew and bandwidth mismatch between the multiplying digital-to-analog converter and the comparator input paths in the first stage, which brings a serious design challenge. This brief presents a novel background calibration technique for these offsets. First, the comparator’s static offset and dynamic offset are discussed and analyzed. Then, a new evaluation technique is proposed to synchronously extract the values of the static offset and dynamic offset through the residue output at decision points. In this brief, the new calibration method is validated using behavioral models. The effective number of bits is improved from 5.04 bits to 11.96 bits, while the spurious free dynamic range is improved by 50.7 dB from our simulation. Thanks to the background calibration, comparator offset errors exceeding the built-in redundancy of the architecture become acceptable. The proposed method relaxes comparator design requirements effectively. More importantly, the calibration can maximize the input frequency of the SHA-less pipelined ADCs.