Back-Gate Effect on <inline-formula> <tex-math notation="LaTeX">$R_{\mathrm {{\mathrm{{\scriptscriptstyle ON}},sp}}}$ </tex-math></inline-formula> and BV for Thin Layer SOI Field p-Channel LDMOS

Abstract

The Backgate (BG) effect on specific ON-resistance ( $R_{{{\mathrm{{\scriptscriptstyle ON}},\rm sp}}})$ and breakdown voltage (BV) for the thin layer Silicon On Insulator (SOI) field p-channel lateral diffusion MOS (pLDMOS) are investigated in this paper. BG-induced dual conduction mode for the thin layer SOI field pLDMOS is revealed, which includes drift and accumulation conduction. Hole accumulation layer induced by BG voltage ( $V_{\rm BG})$ provides extra charges, resulting in a $R_{{{\mathrm{{\scriptscriptstyle ON}},{\rm sp}}}}$ reduction. An expression of equivalent $R_{{{\mathrm{{\scriptscriptstyle ON}},{\rm sp}}}}$ is given to describe the dependence of $R_{{{\mathrm{{\scriptscriptstyle ON}},{\rm sp}}}}$ on $V_{\rm BG}$ . Simultaneously, $V_{\rm BG}$ impacts strongly on BV, inducing three breakdown mechanisms: surface breakdown, bulk breakdown, and punchthrough breakdown. For surface breakdown, a positive linear dependence of BVs on $V_{\rm BG}$ is given with consideration to multiple $_{_{}}$ field plates (MFP). BV of −366 V and $R_{{{\mathrm{{\scriptscriptstyle ON}},{\rm sp}}}}$ of $7.5~\Omega \cdot $ mm $^{2}$ for the thin layer SOI field pLDMOS are achieved experimentally at $V_{\rm BG} = -200$ V.