Abstract
The back gate (BG) induced breakdown mechanisms for thin layer SOI Field P-channel LDMOS (FPLDMOS) are investigated in this paper. Surface breakdown, bulk breakdown and punch-through breakdown are discussed, revealing that the block capability depends on not drain voltage (Vd), but also BG voltage (VBG). For surface breakdown, the breakdown voltage (BVs) increases linearly with VBG increasing. An expression of BVs on VBG is given, providing a good fitting to measured and simulated results. Bulk breakdown with a low breakdown voltage is attributed to high VBG. VBG induces depletion in n-well, giving rise to punch-through breakdown. A design requirement for the thin layer SOI FPLDMOS is proposed that breakdown voltages for the three breakdown mechanisms are compelled to be higher than the supply voltage of switching IC.
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