250 V Thin-Layer SOI Technology With Field pLDMOS for High-Voltage Switching IC

Abstract

A 250 V thin-layer SOI technology based on a 1.5- $\mu \text{m}$ -thick SOI layer is developed for high-voltage (HV) switching IC. HV thin-layer silicon on insulator (SOI) field p-channel LDMOS (pLDMOS) with thick gate oxide layer, SOI RESURF n-channel LDMOS (nLDMOS) with thin gate oxide layer, and low-voltage CMOS are monolithically integrated. Compared with the conventional SOI technology integrating field pLDMOS, the thickness of SOI layer is reduced from above 5 $\mu \text{m}$ to only 1.5 $\mu \text{m}$ . The field implant (FI) technology is adopted to eliminate channel discontinuity underneath the bird’s beak and achieve shallow junction depth to avoid back gate (BG) punchthrough breakdown for the field pLDMOS. A BG punchthrough model is presented with simulation results. The field pLDMOS with breakdown voltage (BV) of −329 V and RESURF nLDMOS with BV of 338 V are experimentally realized. A 250 V switching IC using the field pLDMOS and RESURF nLDMOS as the level-shift and the output stage is also presented based on the developed thin-layer SOI technology.