Abstract
At advanced technology nodes, complex interactions between layout features and the process can lead to manufacturability issues that reduce yield. Due to the huge number of layout geometries inherent to random logic, logic-only test chips are increasingly employed during yield ramp. This work describes a design methodology that incorporates complex layout geometries into an optimally testable full-flow logic test chip. Experiments comparing properties among test-chip, benchmark, and actual product designs demonstrate the efficacy of the methodology. Specifically, our test chips achieve 100% coverage for various fault models, and on average, incorporate the layout geometries of interest while being 96% less layout area and 63% less wire length compared to various benchmark and product designs.
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