Rapid Yield Learning with Effective Integration of FMEA design for DOE on Test Chip

Abstract

Abstract As semiconductor technology advances from one node to the next, fabrication also becomes increasingly challenging to ramp up production with the most desirable yield and reliable product in a timely manner. At an advanced technology node such as 65nm, the interaction between product design, process margin, and process equipment continues to limit the product yield and reliability performance. Traditional methods, which usually rely on sequential feedback of each experimental lot, require too many learning cycles to achieve target performance, yield, and reliability levels. This paper describes a methodology that potentially accelerates the progression of identifying process and product-design interactions and marginalities during the development stage. It demonstrates the successful application of a failure mode effect analysis design design-of-experiments reticle for extracting process-design interaction information. This approach provides insights to early learning cycles in achieving accelerated critical learning for yield and reliability improvements.