On designing two-dimensional scan architecture for test chips

Abstract

Real silicon reveals a lot about how new silicon processes work, so test chips are particularly helpful for the semiconductor manufacturers to evaluate a new technology. Traditionally, semiconductor manufacturers relied only on SRAM test chips for ramping up, qualifying and monitoring new semiconductor fabrication processes. Unfortunately, the transistor and circuit geometries used in an SRAM test chip represent only a small fraction of the transistor and circuit geometries found in a real product [BHA98]. In recent years, logic test chip that narrows the gap between the SRAM chips and the real products are used extensively [BHA98] [HES07] [KAR08]. The logic test vehicle is more representative of real product, but may not be as easily testable and diagnosable as the SRAMs. The logic test chips must capture information related to device and interconnect variability, including systematic and random variations, as well as manufacturing features used in lithography, thermal, stress, proximity effects, and they must use all potentially to-be-used library cells. The logic test chips will help manufacture to incorporate silicon-accurate models and enhanced the manufacturing process. In the past, logic test chips are a small function design that contains as more manufacturing features as possible. As for the test chips, the functionality of a chip does not matter. It is required that the test chip must be designed to cover all manufacturing features. It would be feasible if we can design a test chip with many scan cells such that each scan cell contains some manufacturing features to be used, and all scan cells cover all manufacturing features. Testing such a test chip becomes testing all scan cells and their interconnections. In case a failure occurs, diagnosis down to a scan cell can be easily achieved if we use some special scan architectures. In this paper we present the concept of a two-dimensional scan architecture that makes testing and diagnose down to defective scan cells more easily.