Automatic post-layout flow validation tool for Deep Sub-micron process design kits

Abstract

This paper presents a novel automated post-layout flow validation tool to intensively test the MOSFETs and passive components in 32nm, 28nm and 22nm Process Design Kits (PDK). Benchmark circuits, such as, ring oscillator, logic circuits and passive delay circuits, are automatically generated, LVS (layout versus schematic) checked, extracted and simulated in multiple Model/LVS/Parasitic extraction(PEX) test flows. By using the proposed tool, the delay differences (deltas) between the different test flows are cross verified to assure the functionality and accuracy of Model, LVS and PEX before PDK release. Combined with field solver validation, the automated post-layout flow validation significantly improves the quality and reduces the development time of Deep Submicron (DSM) PDKs.