Using EDA Tools to Push the Performance Boundaries of an Ultralow-Power IoT-VCO at 65nm

Abstract

Voltage-controlled oscillators (VCOs) embedded in state-of-the-art radio-frequency (RF) integrated circuit (IC) multistandard transceivers must comply with extreme ultralow power requirements for modern IoT applications. However, due to the countless tradeoffs that must be considered, their manual design hardly approaches the full potential that a certain topology can achieve at advanced integration nodes. In this paper, the design and optimization of a complex IoT-VCO for a 65 nm process design kit (PDK) is fully supported by electronic design automation (EDA) tools. Firstly, a 108-dimensional performance space is optimized, providing 48 sizing solutions where the power consumption varies from 0.145 mW to 0.329 mW on the worst-case corner performance of the worst-case tuning range. Afterwards, the layout-versus-schematic (LVS) correct layout of each solution is automatically generated using a hierarchical Placer and group-based Router. Post-layout validation is carried in all solutions, and, a promising solution with 0.348 mW of worst-case post-layout power consumption is proposed for fabrication.