Abstract

A systematic method for automatic custom layout of analog integrated circuits is presented. This method uses analog circuit recognition and critical net analysis techniques to derive proper layout constraints for analog circuit performance optimization. Constraint-driven analog floorplanning and routing techniques are developed to generate custom layouts which incorporate the layout constraints. This method can be applied to handle a wide variety of analog circuit modules as well as analog subsystems. Experimental results on CMOS operational amplifiers and a comparator are presented. >

Full Text
Paper version not known

Talk to us

Join us for a 30 min session where you can share your feedback and ask us any queries you have

Schedule a call

Disclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.