Automated analog circuits symmetrical layout constraint extraction by partition

Abstract

In this paper, a method to partition a CMOS analog circuit to extract symmetrical layout constraints of the circuit is presented. We implement it as a program that will be apart of an automatic analog circuit layout constraints extraction tool. To find the symmetrical parts in an analog circuit and transform them as layout constraints to the automatic placement/route tool is the main function of the implemented program A partition algorithm similar to that of comparison method once used to verify the circuit layout against the netlist of the circuit is used for our purpose. The labeling/relabeling process of that method is changed by combining the consideration of the direction of signal flow in the circuit. Experimental results demonstrated that our method is sufficient and effective for analog circuit symmetrical layout constraint extraction.