Abstract
An automatic custom analogue IC layout methodology is presented which employs primitive cell recognition, critical net analysis, and self-constructive floorplanning and routing techniques. Based on this methodology, a general-purpose analogue circuit module layout generator, SLAM, has been developed. Given the schematic netlist of an arbitrary analogue MOS circuit module, SLAM can quickly generate a high-quality custom layout to some desired aspect ratio. With a simple extension of the hierarchy, this method can also handle more complex analogue subsystems. Special layout constraints are automatically analysed for each analogue circuit and properly incorporated into the layout generation on each level of the circuit hierarchy to achieve both high performance and overall area efficiency. Experimental results on common analogue VLSI building blocks such as operational amplifier, comparator and neural circuit modules are presented.
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