Abstract
The increasing emphasis on reducing the defect level of shipped memory parts (current targets are 10 ppm) demand a very high fault coverage of memory tests. Deterministic tests have the advantage of a 100% fault coverage for the targeted faults. However, with each new technology, new layout and new fabrication process, new types of defects will show up; the probability of occurrence of these defects may vary during the time period these parts are produced. This demands for a test strategy whereby tests can be changed/added during the production process of the part. Pseudo-random tests are tests, applied externally or as a BIST, which can be parameterized (mainly via the test length) to detect newly discovered defects. The determination of the test length, for a given fault model, type of pseudo-random test and a given escape probability, is a very complex process. This paper describes a mechanism for automating this process.
Published Version
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