Automated Correctness Condition Generation for Formal Verification ofSynthesized RTL Designs

Abstract

High-level synthesis tools generate register-transfer level designs from algorithmic behavioral specifications. The high-level synthesis process typically consists of dependency graph scheduling, functional unit allocation, register allocation, interconnect allocation and controller generation tasks. Widely used algorithms for these tasks retain the overall control flow structure of the behavioral specification allowing code motion only within basic blocks. Further, high-level synthesis algorithms are oblivious to the mathematical properties of arithmetic and logic operators. Selecting and sharing of RTL library modules are solely based on matching uninterpreted function symbols and constants. Many researchers have noted that these features of high-level synthesis algorithms can be exploited to develop efficient verification strategies for synthesized designs. This paper reports a verification technique that effectively exploits these features to achieve efficient and fully automated verification of synthesized designs and its incorporation in a high-level synthesis tool. In our technique, a correctness condition generator is tightly integrated with a high-level synthesis tool to automatically generate (1) formal specifications of the behavior and the RTL design including the data path and the controller, (2) the correctness lemmas establishing equivalence between the synthesized RTL design and its behavioral specification, and (3) their proof scripts that can be submitted to a higher-order logic proof checker without further human interaction. This approach is based on the identification, by the synthesis tool during the synthesis process, of the binding between critical specification variables and critical registers in the RTL design, and between the critical states in the behavior and the corresponding states in the RTL design. We have implemented our verification technique in conjunction with a relatively mature high-level synthesis tool. We report experimental results indicating the effectiveness of the proposed technique and summarize our ongoing work to further strengthen it.