Attentional Transfer is All You Need: Technology-aware Layout Pattern Generation

Abstract

Having a set of comprehensive VLSI layout patterns is important in researches and applications of design for manufacturability (DFM). However, due to the complexity of the manufacturing process, a large and diverse layout pattern library is usually not available, especially during the early stages of the next technology generation, and this will slow down the technology node development. Many previous pattern generation methods rely on complex rule-based manual guidance or a massive number of existing patterns in the new technology node for learning, which are both costly and with limited availability. Instead of requiring these expensive resources, we propose an attentional transfer-based framework, named CUP-EUV, learning to reuse knowledge from previous technology nodes that should have reserved an enormous amount of layout resources. With the guidance of transferred knowledge, a pattern generation model can be trained by only a small number of patterns from the expensive EUV designs. Experiments show that our model can generate new patterns with much higher performance than the state-of-the-art approaches.