Layout pattern generation and legalization with generative learning models

Abstract

VLSI layout patterns plays an important role in various research in Design for Manufacturing (DFM), such as optical proximity correction, lithography hotspot detection and so on. However, a large and diverse layout pattern library is usually not available during development stages due to the long and iterative technology life cycle, which brings potential difficulties to related research and slows down the development process. Although some previous works managed to enlarge pattern libraries with different solutions, there are still many challenges on generating complex DRC-clean two-dimensional patterns with specific styles. To address this problem, we explored the capability of generative machine learning models to learn the inherent distribution of a given set of non-trivial layouts for synthesizing diverse and realistic layout patterns with little manual guidance. For this purpose, we propose CUP, the CU pattern generation and legalization framework, which consists of two learning-based modules for pattern topology generation and design rule legalization respectively. Experiments show that CUP can generate diverse legal layout patterns which are comparable to actual design layouts in terms of resemblance in style and validity.