Asynchronous high throughput NoC under high process variation

Abstract

Asynchronous NoC switch is proposed as a robust design to mitigate the impact of process variation. Asynchronous and synchronous network on chip design are implemented to evaluate the impact of process variation on the network throughput. Network on chip interconnects and clock distribution network are considered under process variation with the advance in technology. The variation in logic and interconnect are included to evaluate the delay and throughput variation with different technologies. The throughput negligibly decreases under high process variation conditions in asynchronous NoC switch, while rapidly decreases by up to 25% in synchronous design at the same variation conditions.