Abstract

Silicon photonic devices and integrated circuits are vulnerable to fabrication-induced process variations (a.k.a. fabrication non-uniformity). Designing silicon photonic integrated circuits (PICs) for wavelength-division multiplexing (WDM)-based applications requires a careful consideration of fabrication-induced process variations. While numerical simulations (e.g., FDTD) help predict a device's behaviour after its fabrication, applying such methods to large-scale PICs is not feasible as they impose an extremely high computation cost. In this work, we present a computationally efficient and yet accurate bottom-up approach to study the impact of fabrication-induced process variations on passive silicon photonic devices and integrated circuits. The bottom-up approach starts by studying the impact of process variations on the effective and group indices of strip waveguides (component level). Leveraging the analytical models at the component level, we evaluate the tolerance of microresonator (MR)-based add-drop filters and switches under different process variations (device level). We specifically consider the variations in the top silicon thickness and waveguide width. Compared with time-consuming numerical simulations, we demonstrate that our proposed method is highly efficient in terms of accuracy and computation time: an error rate smaller than 1% and a speed-up greater than 100× are achieved. Our study also involves the design, fabrication, and analysis of several identically-designed fabricated MRs, for which we evaluate the within-die variations and also quantify the resonance wavelength shifts. Moreover, we indicate a strong correlation among the resonance wavelengths of the MRs in proximity as well as those which are not in close proximity. Our proposed method helps evaluate the impact of process variations on the performance of large-scale PICs, determining power penalties required to trim/tune (e.g., thermal tuning) faulty devices in such systems.

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