High Throughput Asynchronous NoC Design under High Process Variation

Abstract

Asynchronous switching is proposed as a robust design to mitigate the impact of process variation in Network on Chip (NoC). Circuit analysis is used to evaluate the influence of process variation on both synchronous and asynchronous designs. The impact of process variation is evaluated on different NoC topologies. Network on chip interconnects and clock distribution network are considered under process variation with the advance in technology. The variation in logic and interconnect are included to evaluate the delay, throughput and leakage power variation with different NoC topologies. In addition, the delay and throughput variation are evaluated for clock distribution network. For asynchronous NoC design, the throughput negligibly decreases under high process variation conditions in different NoC topologies. The throughput variation for synchronous design in all topologies rapidly decreases by up to 25% at the same variation conditions.