Asynchronous hardware implementations for crypto primitives

Abstract

Cryptography plays a major role in all the modern applications, where the Galois field (GF) arithmetic circuits are inevitable. In this paper, asynchronous GF(2m) and m-bits GF(p) multiplier, inverter, and exponentiator are proposed, where the hardware is repeatedly reused for m iterations without synchronous registers (m=log2p). Also, this paper proposes an asynchronous implementation of GF(2163) affine coordinate based ECC scalar multiplication that includes the point addition and point doubling. Here, the inverse is calculated using Fermat's Little theorem. The entire scalar multiplication is done using only two GF(2163) multipliers without any hardware registers that are replaced by a completion detection logic. The same proposed logic is used in the asynchronous 128-bits AES design. The power dissipation of these proposed designs are much less than the existing designs due to the elimination of synchronous registers. Our proposed asynchronous logic is free from the glitches and metastability. The proposed asynchronous GF(216) multiplier design achieves 99.6% of improvement in switching power reduction than scalable Montgomery [5] based multiplier using 45 nm CMOS technology.