Assessment of interface traps in In 0.53 Ga 0.47 As FinFET with gate‐to‐source/drain underlap for sub‐14 nm technology node to impede short channel effect

Abstract

Silicon fin field-effect transistor (FinFET) devices with gate–source/drain underlap fin length (Lun) structures have been used for effective reduction in short channel effects (SCEs) from many years. Here, investigations have been performed on the FinFET structure with In0.53Ga0.47As material. Three-dimensional technology computer-aided design simulations for 14 nm channel length In0.53Ga0.47As FinFETs with underlap have been conducted by incorporating various effects to analyse the influence of interface traps on the device. The dominance of traps is investigated on SCE and intrinsic delay to assess the trend on underlap devices. The impact on threshold voltage and on current due to metal gate work function (MGWF) variation has been also demonstrated. Simulations have been carried out for Lun = 0, 3, 6, and 9 nm with interface trap density of 1012 and 1014 cm–2 eV–1. Improvement in the subthreshold swing (SS) is observed as the Lun increases but at the cost of intrinsic delay. However, the improvement in SS after Lun = 6 nm is nearly constant. It has been also observed that the relative standard deviation of the threshold voltage and on current variation due to MGWF variation improves as the Lun increases till 6 nm after that this improvement is not very significant.