Assessing SET sensitivity of a PLL

Abstract

Single Event Transients (SETs) are soft errors that occur in CMOS circuits as the result of radiation effects. An SET consists in the generation of a short current pulse in the active area of a transistor. In a digital circuit, these events provoke a transient voltage pulse while in analog circuits the effect depends on the kind of affected component. Assuring the fault tolerance behavior under SETs of integrated circuits is mandatory in case of safety-critical applications. Phase-locked loop (PLL) blocks are very critical components in applications working in harsh environments, like space applications. They are used to generate high accuracy oscillatory signals, and a transient error could produce a failure of the system. This paper explains a method to assess the sensitivity of a PLL under SETs. Experimental results allow the designer to detect the weakest nodes in order to, eventually, perform selective hardening and appropriate hardened solutions.