SET Detection and Compensation and Its Application in PLL Design

Abstract

This paper presents a new charge compensation (CC) scheme to mitigate single event transient (SET) effect at the output node of the charge pump (CP), the most SET vulnerable node in a Phase-Locked Loop (PLL). It achieves a 4X less SET-induced voltage disturbance at the ring oscillator control node as well as a faster PLL recovery time. During the normal operation, the CC circuit does not affect the PLL dynamics. Its control block ensures that the CC circuit is enabled only when the CP output voltage is disturbed by SET strikes. This avoids the conflict between SET charge compensation and normal PLL phase correction. The PLL covers a 12.5 MHz to 500 MHz tuning range with a root-mean-square (RMS) jitter of 4.9 ps. It consumes 21.5 mW of power under a 1.5 V power supply. The CC circuit consumes 4.5 mW power and occupies 5.3% of the PLL area.