Assembly Solutions for Cost-Effective Heterogeneous Integration with Disparate Die Types

Abstract

The semiconductor industry is driving to enable high volume integration of disparate die types via Heterogeneous Integration. These die can come from a range of wafer sizes fabricated in different technology nodes. This emerging package type creates new challenges regarding assembly efficiency and yield. Traditionally, flip-chip assembly process flows have utilized a single placement tool for the placement of the single die type onto the target substrate. For applications with multiple die types, a series of placement tools have been configured in a production line, with each tool dedicated to the placement of a specific die type. This paper and presentation explore the implications of this type of solution in the era of Heterogeneous Integration. Impacts on product yield, throughput, manufacturing efficiency, and overall cost of assembly will be explored for a broad range of Heterogeneous Integration die configurations. Based on a sensitivity analysis for the range of die types expected in these applications, a novel approach to optimization of overall assembly economics will be proposed. Appropriateness of this novel approach will be explored for a range of packaging solutions, including Flip-Chip, 2.5D, 3D, and Fan-Out.