Assembly and reliability of micro-bumped chips with Through-silicon Vias (TSV) interposer

Abstract

This paper presents the assembly optimization and characterization of through-silicon vias (TSV) interposer technology for two 8 × 10mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> micro-bumped chips. The two micro-bumped chips represent different functional dies in a system-in-package (SiP). In the final test vehicle, one of the micro-bumped chips had 100¿m bump pitch and 1,124 I/O; the other micro-bumped chip had 50¿m bump pitch and 13,413 I/O. The TSV interposer size is 25 × 25 × 0.3mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sup> with CuNiAu as UBM on the top side and SnAgCu bumps on the underside. The conventional substrate size is 45 × 45mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> with 1-2-1 layer configuration, a ball-grid array (BGA) of 1mm pitch and a core thickness of 0.8mm. The final test vehicle was subjected to MSL3 and TC reliability assessment. The objective of this paper was to incorporate two 8 × 10mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> micro-bumped chips into TSV interposer. The micro-bumped chips should have no underfill voiding issue and the whole package should be able to pass moisture sensitivity level 3 (MSL3) and thermal cycling (TC) reliability assessment. To achieve this objective of incorporating micro-bumped chips into the TSV interposer, the challenges were small standoff height/ low bump pitch of the micro-bumped chip, underfill flowability and its reliability performance. To overcome these challenges, different types of capillary flow underfill, bump layout designs and bump types were evaluated and a quick reliability assessment was used to select the materials and test vehicle parameters for final assembly and reliability assessment.