ASIC Primitive Cells in Modified Gated Diffusion Input Technique

Abstract

Power dissipation has become a prime constraint in high performance applications, especially in clocked devices like microprocessor and portable devices. Optimizations for the ASIC cells are crucial in order to improve the performance of various low power and high performance devices. The design criterion of primitive cells is usually multi-fold. Optimization of several devices for speed and power is a significant issue in low-voltage and low-power applications. These issues can be overcome by incorporating Gated Diffusion Input (GDI) technique. This paper mainly presents the design of primitive cells like AND, OR, NAND, NOR, MUX, XOR and XNOR cell in Modified Gate Diffusion Input Technique. This technique allows reducing power consumption, delay and area of digital circuits, while maintaining low complexity of logic design. Delay and power has been evaluated by Tanner simulator using TSMC 0.250 technologies considering minimum power design. The simulation results reveal better delay and power performance of proposed primitive cells as compared to existing GDI cell and CMOS at 0.250μm CMOS technologies.