New low power delay element in self resetting logic with modified Gated Diffusion Input technique

Abstract

Low power design has become one of the primary focuses in digital VLSI circuits, especially in clocked devices like microprocessor and portable devices. Optimization of several devices for speed and power is a significant issue in low-voltage and low-power applications. These issues can be overcome by incorporating Gated Diffusion Input (GDI) technique. Now-a-days dynamic circuits are becoming increasingly popular because of the speed advantage over static CMOS logic circuits. A fundamental difficulty with dynamic circuits is the monotonicity requirement and difficulties like charge sharing feed through, charge leakage, single-event upsets, etc. These issues can be eliminated using Self-reset logic (SRL). This logic provides a design solution where the clocking overhead is minimized. So the tradeoff between speed and power can be achieved through SRL and GDI technique. A new family of Modified self-reset logic (SRL) cells implemented with modified GDI technique is presented in this paper. The implementations proposed in this work are clocked storage element like D-FF in SRL with Modified Gate Diffusion Input Technique. This technique allows reducing power consumption and delay of digital circuits, while maintaining low complexity of logic design. Delay and power has been evaluated by Tanner simulator using TSMC 0.250μm technology. The simulation results reveal better delay and power performance of proposed delay elements as compared to existing dynamic, GDI cell and CMOS at 0.250μm technology.