Abstract
Shallow junction formation technology by arsenic ion implantation is evaluated from the viewpoint of practical application to the coming VLSI's. Carrier profile, residual defect profile, and electrical characteristics are examined as functions of acceleration energy, dose, annealing conditions, and surface oxide thickness. The carrier profile is determined mainly by both arsenic ion amount in the substrate layer and annealing conditions. The residual defect profile is determined by implantation energy and surface oxide thickness. It is necessary to implant arsenic ions shallower than the resulting carrier profile, to obtain arsenic ion‐implanted junctions with acceptable electrical characteristics. A junction diode, with junction depth as shallow as 0.16 μm is fabricated according to this principle, and is ascertained to have acceptable electrical characteristics.
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