ARM-FPGA-based platform for reconfigurable wireless communication systems using partial reconfiguration

In the past years dynamic partial reconfiguration (DPR) has been established as a well-known technique for systems featuring a field programmable gate array (FPGA). Systems-on-Chip (SoC) with an ARM processor ease the utilization of DPR and motivate its implementation to make use of the obvious advantages, such as the reduction of area, power and the acceleration of reconfiguring the FPGA. Nonetheless, the development process for SoCs is still a complex and time consuming task, especially for those designs using DPR. Xilinx counters this complexity with the introduction of their new high-level tools, namely the SDx Development Environment. The SDSoC Development Environment accelerates the development of designs running on Zynq 7000 devices by only using C/C++ applications as input. Unfortunately, this high-level workflow does not incorporate DPR. This paper shows an approach on how to use DPR in Xilinx SDSoC. Thus an application specific design can benefit from both the high-level workflow and the advantages of DPR. We show that our approach to DPR in SDSoC accelerates the overall design time and creates a more efficient embedded application. In our use case the dynamic and partial reconfiguration of hardware accelerators takes 10 ms and the hardware-related section of our embedded application is accelerated by a factor of 14 due to DPR.

Recent fixed and mobile wireless communication systems have attracted researchers to propose new techniques and methodologies that greatly improve performance. For example, adaptive techniques have improved the wireless channel efficiency while decreasing the overall power consumption. They consist in reconfiguring parts of the global system automatically according to different parameters. In parallel, circuit technology has also considerably evolved. One example is Field Programmable Gate Arrays (FPGAs) that are now suitable for implementing the physical layer of most complex wireless communication systems. This has been made possible thanks to their high level of performance, flexibility, and bit-level programming. In these devices, the Dynamic Partial Reconfiguration (DPR) constitutes a well known technique for reconfiguring only a specific area within the circuit. This technique offers efficient resource utilization, reduced power consumption and permits the optimization of the configuration time. In our work, we benefit from this technology to implement a wireless communication system in hardware. Hardware reconfiguration is performed automatically according to adaptive decision processes running on top of a micro-kernel that manages partial reconfiguration. The system is implemented on a ZedBoard which features a Xilinx Zynq 7000 System on Chip (SoC).

Dynamic Partial Reconfiguration (DPR) of SRAM-based Field Programmable Gate Arrays (FPGAs) becomes a demanding feature by many applications for its ability to add more flexibility over runtime phase. Recently, implementation designs which utilize DPR are easier than before. However, techniques that FPGAs use to perform DPR (like ICAP and JTAG) encounter a performance bottleneck; only one DPR is allowed at a time. In this paper, we present a state-of-art NoC-based FPGA simulator, which supports partial dynamic reconfiguration simulation. Design limitations and performance degradations of using DPR on NoC-based FPGA are estimated using NoC-DPR simulator. Experiments are carried out using NoC-DPR simulator to measure the reconfiguration time overhead by increasing number of simultaneous DPRs on FPGA fabric. It is shown that the overhead of reconfiguration time is increased exponentially with increasing the number of carried out simultaneous DPRs. However, DPR of NoC-based FPGA can enhance performance compared to DPR of normal FPGAs with some trade-offs.

This paper describes the usage of Field Programmable Gate Array (FPGA) to explore reconfiguration to help out in the field of Biomedical Applications. The FPGA is reconfigured at runtime to analyze parameters like temperature, heart rate, blood pressure of patients and identify the conditions as normal, critical or emergency. According to the applications implemented there are two ways used to approach the Dynamic Partial Reconfiguration (DPR) practically. First is to configure the FPGA before reconfiguration and this part is known as static or fixed programming. Next part we reconfigure the FPGA again and run the program this is known as the partial reconfigurable part of the system. Basically initially two nodes are taken a temperature sensor along with the smoke sensor, after reconfiguration two more nodes are incorporated photo detector and Infrared Radiation (IR) sensor. Runtime reconfiguration is done to monitor parameters like blood pressure, heart rate, oxygen saturation etc. The runtime reconfiguration is carried out where we allow the user to enter the patient number and FPGA displays the condition of that particular patient at runtime. Hence a particular patients output can be observed. For which we can have n input patients and we can get the monitored continuous status of the nth patient. Such type of the program can be useful to send data wireless to the doctor and patient can be checked for the particular parameter. The outcomes involve displaying normal condition at temperature 98 °F & respiration rate of 17 inhalations per minute, displaying critical condition at temperature 102 ° F & respiration rate of 30 inhalations per minute, displaying emergency condition at temperature 96 ° F & respiration rate 127 inhalations per minute, emergency condition for the heart rate and the oxygen saturation levels of the patient while the temperature module keeps on function but not displayed. Also displayed is DPR for heart rate 70 bpm and oxygen saturation of 95 % indicates the normal condition, critical condition in DPR for heart rate 35 bpm and oxygen saturation at 85 %, emergency condition in DPR for heart rate 165bpm and oxygen saturation at 60%. Normal condition in DPR for bpl 85 mmHg and bph 120 mmHg. The blood pressure of patient is monitored as normal condition in DPR for bpl 88 mm Hg and bph 108 mm Hg. Normal condition in DPR18 for bpl 94 mmHg and bph 150 mmHg. The above work can be successfully incorporated for patient health monitoring and can be further improved by sending wirelessly the data to a central hub if the patient’s location is at some remote place. Keywords: Application Specific Integrated Circuits (ASIC), Dynamic Partial Reconfiguration (DPR), ElectroCardioGraphy (ECG), Field Programmable Gate Array (FPGA), Head Of Bead (HOB), Hardware Descriptive Language (HDL), Internet Content Adaptation Protocol (ICAP), Integrated Synthesis Environment (ISE), Joint Test Action Group (JTAG), Joint Tactical Radio System (JTRS), Look Up Table (LUT), Partial Reconfiguration Modules (PRM), Patient Monitoring System (PMS), Wireless Sensor Network (WSN)

Technology down-scaling and platform-based designs have enforced a number of application and architecture trends for system-on-chip (SOC) designs. A modern SOC is now a multi-functional machine that can execute a large number of complex applications by using tens or even hundreds of intellectual properties (IPs). Meanwhile, due to a number of constraints, e.g., short time to market, fickle market demands, and high non-recurring engineering (NRE) costs to name a few, Field Programmable Gate Arrays (FPGAs) have gained popularity to implement SOC designs. The applications in an SOC can be dynamically started and stopped thus forming multiple use-cases. The applications can also have diverse Quality-of-Service (QoS) constraints ranging from non real-time to soft, firm, and hard real-time constraints. At the same time the IP cores in an SOC are heterogenous in nature and run at diverse clock frequencies. The IPs can be microprocessors, DSP slices, memories, and ALU units, etc. The increasing number and diversity of applications and IPs require a powerful onchip communication architecture for quick integration and appropriate QoS. In contemporary FPGAs the onchip interconnect would be soft, i.e., programmed in the configurable fabric. The above-mentioned application and architecture trends have triggered a series of problems. (1) An increasing number of applications on an FPGA often requires dynamic reconfiguration of an application, which in turn can produce interference with other running applications. (2) The increasing complexity of an application may mean that it can not be mapped entirely on the FPGA, which in turn can encounter loss of state of data during intra-application dynamic partial reconfiguration. (3) The diverse natures of applications make it difficult to fulfill the Quality-of-Service constraints of an application. (4) Similarly, it is hard to achieve (physical) timing closure in an SOC, because of the increasing number and diversity of the IP cores. (5) The technology downscaling leads to FPGA architectures that are more prone to faults, e.g., configuration memories and logic elements in an FPGA can be stuck at a particular value. (6) Because communication architecture and IPs are both mapped as soft IPs in the same logic plane of the FPGA, their placement has many restrictions to allow for dynamic partial reconfiguration. In this thesis, we aim to address the above-mentioned problems by proposing the architecture and design flow of a new FPGA. As the main contribution of the thesis, we propose the FPGA architecture with a hardwired network on chip (HWNoC), and multiple test, configuration, and functional regions (TCFRs). We call it hardwired, because the NoC in an FPGA is built in silicon and not by using the reconfigurable elements. By having a HWNOC we can have a globally asynchronous locally synchronous (GALS) environment, which in turn ensures that data is not lost during inter-IP communication. The HWNOC separates the communication and computation in two disjoint planes, which alleviates restrictions on the placement of IPs. As the second contribution of the thesis, we show how we can use the HWNOC to transport unified test, configuration, and functional data to TCFRs, for testing, faster configuration, and interference-free communication during execution of applications. As the third contribution of the thesis, we demonstrate that how the proposed design flow ensures predictable application behavior by fulfilling the QoS constraints. We also present a 3-tier reconfiguration model that uses the HWNOC, which ensures contention-free communication at architecture level, to overcome the problems of interference and state-loss during inter-application and intra-application reconfiguration respectively. Another contribution of the thesis is that it proposes a non-intrusive test methodology that uses the HWNOC as a test access mechanism to test the presence of faults reliability of FPGA architecture. In other words, the proposed methodology makes sure that applications are always reconfigured and executed on a reliable region of an FPGA, and without effecting the other running applications.

In recent years, the development of mobile terminals such as smartphone is remarkable. However, along with its evolution, there is a problem of increasing the cost and the power consumption by increasing the chip size of system-on-chip (SoC) in terminal. One of approaches tackling this problem is to take advantage of Dynamic Partial Reconfiguration (DPR) on reconfigurable devices. In DPR, large-scale circuits can be time-divisionally executed on a small die in SoC. In other words, cost reduction and power saving can be achieved with the minimum necessary chip size. In this research, we attempt to show a performance merit of DPR by performing a time division execution of a large scale circuit on small portion in a reconfigurable device, Field Programmable Gate Array (FPGA). In addition, we try to estimate how much cost can be reduced in the current general FPGA by using DPR.

The ability of the Field Programmable Gate Arrays (FPGAs) to reconfigure themselves makes them stand out and a preferred choice while designing an embedded system. The basic hardware architecture of FPGAs is the reason behind the availability of this unique feature. Most of the SRAM-based FPGAs supports partial reconfiguration (PR) feature. Many complex algorithms can be implemented using dynamic partial reconfiguration on FPGAs while occupying minimum possible area. Many applications implemented on FPGAs do not execute in a parallel fashion where different modules of the application are implemented over dedicated part of the hardware. Most of the time these modules are dependent on each other's result therefore they cannot execute in parallel and leave a big amount of the FPGA area sitting idle most of the execution period. We propose a framework based on Dynamic partial reconfiguration, which allows scheduling the execution of multiple logic designs over the same area of FPGA fabric. In order to validate the proposed methodology, JPEG compression has been implemented as a case study Zynq-7000 SOC using both proposed framework and a single static implementation. In addition, the effectiveness of the proposed methodology is quantified by comparing the FPGA resource utilization of the original JPEG compression engine design and that of the partial re-configurable prototype. The results indicate a significant reduction in hardware resource utilization where 34%, 39% and 66% reduction has been achieved in Slice LUTs, Slice Registers and DSP blocks respectively.

Reconfigurability of SRAM-based Field Programmable Gate Arrays (FPGAs) is the most powerful feature over ASIC designs. Dynamic Partial Reconfiguration (DPR) emphasizes this feature by adding more flexibility over runtime phase. Xilinx Virtex family of FPGAs provides four techniques to perform DPR; SelectMAP, Serial mode, JTAG, and ICAP. In this paper, each of these techniques is reviewed, evaluated, and tested using Convolutional encoder, an essential block from Software Defined Radio (SDR) system, which becomes the most promising application for DPR. Experiments are carried out using Xilinx Virtex 5 kit "XUPV5-LX110T" to measure the trade-offs between performance and area-overhead by adding reconfiguration controller on/off FPGA fabric. It is shown that the performance of each interface is independent of design resource, but proportional only with partial reconfiguration region selection that had been chosen at design place and route phase.

Heterogeneous system-on-chips (SoC) that include both general-purpose processors and field programmable gate arrays (FPGAs) are emerging as very promising platforms to develop modern cyber-physical systems, combining the typical flexibility enabled by software with the speedup achievable by custom hardware accelerators. Furthermore, the dynamic partial reconfiguration (DPR) capabilities of modern FPGAs make such platforms even more attractive, offering the possibility of virtualizing the FPGA area to support several hardware accelerators in time sharing. However, heterogeneous platforms originate considerable challenges in the design and development process of applications, especially if timing and energy constraints are concerned. The FRED framework has been recently proposed to support the development of real-time applications upon such platforms, using a static slotted-based partitioning of the FPGA area to ensure predictable delays when managing custom hardware accelerators by DPR. This paper addresses the problem of designing a suitable FPGA partitioning to support the execution of a real-time application within the FRED framework. The problem is formulated as a mixed-integer linear program that is in charge of (i) designing the size of the slots (in terms of FPGA resources), (ii) allocating hardware tasks to the slots, and (iii) selecting which hardware tasks must be statically allocated to the FPGA, while ensuring bounded worst-case response times on the tasks.

NoC-DPR: A new simulation tool exploiting the Dynamic Partial Reconfiguration (DPR) on Network-on-Chip (NoC) based FPGA

Advances in the configurable logic fabric's architecture, together with the increasing hard-wired integration of commonly used cores such as giga-bit I/O transceivers, multipliers and processors suggests that statically configured FPGA (field programmable gate array) platforms will continue to become more competitive and therefore gain further market share at the expense of the ASIC. In addition, the Semiconductor Association predicts that the percentage area of memory in a system-on-chip (SOC) will continue to increase, with 70% of a SOC are devoted to RAM by 2005. However, it is not certain whether it is valid to combine these observations and extrapolations to predict the demise of the ASIC as some FPGA vendors believe. One of the main arguments made against this prediction is the size of the silicon are gap between an ASIC solution and an FPGA solution is largely attributed to the area inefficiency of the FPGA configurable logic fabric. Dynamic partial reconfiguration can help significantly reduce this are inefficiency gap.

With applications to become increasingly compute- and data-intensive, requiring more processing power, many Internet of Things (IoT) platforms in robots, drones, and autonomous vehicles that implement neural network inference, cryptographic functions or signal processing (e.g., multimedia, communication), employ field programmable gate arrays (FPGAs). At the same time, dynamic partial reconfiguration (DPR) in modern FPGAs enable changing the function of a part of the FPGA by dynamically loading new bitstreams to the logic regions without affecting the function of other parts of the FPGA. This is especially useful to update functions of IoT devices while in operation for bug fixing or functionality adjustments and, more importantly, when these IoT devices integrate low-cost FPGAs that can hardly realize many hard accelerators. To deal with one of the major limitations of using partial reconfiguration in IoT devices, this work introduces techniques to flexibly use DPR, namely, FLEXDPR, by sharing reconfigurable partitions among different accelerator functions and by supporting virtual relocation of these functions. Experimental results on the Xilinx Zynq-7000 platform reveal energy and latency efficiency improvements of about 20%, on average. Overall, the suggested approach can reduce partial reconfiguration overhead while easing the scheduler’s decisions for the deployment of hardware functions throughout time and space in a performance-conscious manner.

Dynamic partial reconfiguration (DPR) technique is a very efficient for low-cost field programmable gate array (FPGA) for realising several application categories like signal processing. The present work demonstrates a generic framework for implementing Software Defined Radio (SDR) based communication system using DPR. The work switches contexts with two partial reconfiguration blocks. Namely spectrum estimation and frequency shift keying (FSK) receiver blocks. The former uses the streaming type fast Fourier transform (FFT) and later uses frequency shifting and filtering stages. The completely developed FSK receiver is simulated using Modelsim. Xilinx Zynq 7010 SoC with DPR is used for implementation. An FSK signal with symbol rate 64 Kbps is used to drive the analogue to digital converter (ADC) input. The work demonstrates novel direction for SDR implementation with DPR for low-area FPGAs. The results shows 45% lesser FPGA-DSP48 slices are used compared to without-DPR. Reduced power dissipation is observed as by-product.

Bioinformatics data tend to be highly dimensional in nature thus impose significant computational demands. To resolve limitations of conventional computing methods, several alternative high performance computing solutions have been proposed by scientists such as Graphical Processing Units (GPUs) and Field Programmable Gate Arrays (FPGAs). The latter have shown to be efficient and high in performance. In recent years, FPGAs have been benefiting from dynamic partial reconfiguration (DPR) feature for adding flexibility to alter specific regions within the chip. This work proposes combing the use of FPGAs and DPR to build a dynamic multi-classifier architecture that can be used in processing bioinformatics data. In bioinformatics, applying different classification algorithms to the same dataset is desirable in order to obtain comparable, more reliable and consensus decision, but it can consume long time when performed on conventional PC. The DPR implementation of two common classifiers, namely support vector machines (SVMs) and K-nearest neighbor (KNN) are combined together to form a multi-classifier FPGA architecture which can utilize specific region of the FPGA to work as either SVM or KNN classifier. This multi-classifier DPR implementation achieved at least ~8x reduction in reconfiguration time over the single non-DPR classifier implementation, and occupied less space and hardware resources than having both classifiers. The proposed architecture can be extended to work as an ensemble classifier.

this paper reviews the state of the technique of field programmable gate array (FPGA) for partial Reconfiguration (PR), design methodologies of Wireless Communication System, such as Multi Carrier Code Division Multiple Access (MC-CDMA) technique has been to be suited for future wireless systems that are expected to provide higher data rates and greater flexibility for the services of voice, data, video and Internet to the users due to its property in using the bandwidth in efficient manner. The Software Defined Radio is considered as a wireless system applied by routines so as software. Consequently, the use of SDR allows vehicle manufacturers to familiarize communication applications sustained through cars to appropriate to the standards of the respected country presented in the object oriented programming. FPGAs are playing a very significant role in SDR. However, in modern wireless communication system programs, SDR and CR need to design a wide range of waveforms complex, which it is complicated in design and performance and implementation needs more time. The design of the modulation and demodulation and other signal processing application of PR technique that have the ability to modify blocks of logic dynamically by downloading partial bit files, while the remaining logic is still working without interruption; thus, power consumption and configuration time can be saved for a larger extent. The PR using was allowed to move for fewer or smaller devices as, decrease power and increase system upgradability.